Field of the Invention
The present invention generally relates to video decoder systems, and more specifically, to a low power context adaptive binary arithmetic decoder engine.
Description of the Related Art
Digital video playback represents an important capability for modern digital mobile devices. Video compression and decompression technology is fundamental to enabling efficient playback and use of constrained resources associated with mobile devices. Video information comprises sequential frames of two-dimensional color and intensity information. Uncompressed video information typically represents each pixel of color and intensity information within a frame directly. Compressing the video information typically involves removing redundant or unimportant information within a given frame, and removing redundant or unimportant information between frames. For example, a discrete cosine transform (DCT) may be used to remove two-dimensional spectral information from blocks of pixels that is unimportant to human perception. Motion estimation and compensation serves to remove information that is redundant between frames by representing a new frame in terms of changes relative to a previous frame. A key consequence of removing redundant and unimportant information is that compressed video information typically requires less data than a corresponding sequence of uncompressed video information. The compressed video information typically comprises a structured data stream having certain syntax elements that allow a decompression engine to uniquely parse the structured data stream and recreate a sequence of uncompressed frames, which may then be displayed.
One highly efficient video compression and decompression technique known in the art is the International Telecommunications Union (ITU) recommendation H.264 for advanced video coding for generic audiovisual services, simply “H.264.” This technique organizes compressed video as an ordered data stream comprising a hierarchy of objects, starting with a sequence one or more frames, where a frame comprises one or more slices, and where a slice comprises one or more macroblocks, each of which may comprise one or more sub-macroblock partitions. The hierarch continues so that each sub-macroblock may include one or more blocks, and each a block may include a set of samples, each of which comprises a color and intensity value for an individual pixel. Encoding video information according to H.264 comprises describing video frames based on a set of encoding and compression tools. Such tools are associated with syntax elements comprising the ordered data stream.
One aspect of H.264 comprises entropy coding for certain syntax elements. Entropy coding is a computationally intensive technique for performing lossless compression of repeating vectors of arbitrary bit length. In particular, H.264 implements a technique known in the art as context-based adaptive binary arithmetic coding (CABAC), which may be efficiently implemented directly in logic circuits. A CABAC circuit conventionally operates on a bin of data per iteration to generate a decoded string and a context update to be applied when operating on a subsequent bin of data. In conventional systems implementing H.264, a video decoder pipeline comprises different pipeline stages built from logic circuits that are configured to operate synchronously with respect to the CABAC circuit. Inherent complexity associated with different stages of the decoder pipeline, including a CABAC stage, dictates a maximum operating frequency of the video decoder pipeline. The video decoder pipeline is typically able to operate on a range of video resolutions and formats, each having a different data throughput requirement. The video decoder pipeline needs to be designed to accommodate a certain maximum data throughput based the most demanding video format supported, and each video format having a lower throughput characteristic simply places less overall load on the video decoder pipeline, which is conventionally designed to operate at a fixed speed.
One consequence of implementing a configurable design for the video decoder pipeline based on the maximum data throughput requirement is that the video decoder pipeline is typically overpowered with respect to typical usage cases, leading to superfluous dissipation of power and reduced battery life.
As the foregoing illustrates, what is needed in the art is a technique for improved power efficiency in configurable video decoder pipelines.